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| White Electronic Designs 512K x 64 Synchronous Pipeline NBL SRAM FEATURES Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Seperate +2.5V 5% power supplys for core I/O (VCC + VCCQ) Double Word Write Control Clock-controlled and registered addresses, data I/Os and control signals Packaging: * 119 bump BGA package Low capacitive bus loading WED2ZL64512S DESCRIPTION The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC's 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable are synchronized to input clock. Output Enable controls the outputs at any given time and to Asynchronous Input. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. NOTE: NBL = No Bus Latency is equivalent to the industry ZBTTM devices. FIG. 1 PIN CONFIGURATION (TOP VIEW) A B C D E F G H J K L M N P R T U 1 DQF DQF DQE DQE NC SA SA SA SA18 SA SA SA NC DQD DQD DQC DQC 2 3 4 5 DQF DQF DQF NC DQF DQF DQF NC DQE DQE DQE NC DQE DQE DQE NC NC NC VCCQ VCCQ VCCQ VCC VCC VCC CE# VSS VSS VSS NC VSS WE1# VSS CE2# SSCK OE# NC CE2 VSS WE0# VSS NC VSS VSS VSS VCCQ VCC VCC VCC NC NC VCCQ VCCQ DQD DQD DQD NC DQD DQD DQD NC DQC DQC DQC NC DQC DQC DQC NC 6 DQG DQG DQH DQH VCCQ VCC VSS VSS NC VSS VSS VCC VCCQ DQA DQA DQB DQB 7 DQG DQG DQH DQH NC VCC VSS VSS NC VSS VSS VCC NC DQA DQA DQB DQB 8 DQG DQG DQH DQH NC VCCQ SA SA SA1 SA SA VCCQ NC DQA DQA DQB DQB 9 DQG DQG DQH DQH NC SA SA SA SA0 SA SA SA NC DQA DQA DQB DQB BLOCK DIAGRAM SA 0 - 18 DQ 0 - 31 DQ 32 - 63 A0 - A18 OE# WE# CK CS2# CS2 CS1# OEB WEB_LW CK CS2B CS2 CS1B U1 DQ 0 - 31 512K x 36 A0 - A18 WEB_HW OE# WE# CK CS2# CS2 CS1# U2 DQ 0 - 31 512K x 36 White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTION DESCRIPTION The WED2ZL64512S is an NBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE#) are synchronized to rising clock edges. Output Enable (OE#) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE# is driven low, the write enable input signals WE# are driven high. The internal array is read between the first WED2ZL64512S rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE# must be driven low for the device to drive out the requested data. Write operation occurs when WE# is driven low at the rising edge of the clock. The pipe-lined NBL SSRAM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE# and address are registered, and the data associated with that address is required two cycle later. TRUTH TABLES SYNCHRONOUS TRUTH TABLE CEx# H L L X L L NOTES: WE# X H H X L L OE# X L H H X X CK Address Accessed N/A Current Address N/A N/A Current Address N/A Operation Deselect Read Cycle NOP/Dummy Read Dummy Read Write Cycle NOP/Write Abort 1. X means "Don't Care." 2. The rising edge of clock is symbolized by ( ) 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Voltage on VCC Supply Relative to Vss VIN (DQx) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current WED2ZL64512S ABSOLUTE MAXIMUM RATINGS* -0.3V TA +3.6V -0.3V TA +3.6V -0.3V TA +3.6V -55C TA +125C 100mA *Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS (0C TA 70C) Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage NOTES: 1. All voltages referenced to VSS (GND) Symbol VIH VIL ILI ILO VOH VOL VCC Conditions Min 1.7 -0.3 Max VCC +0.3 0.7 5 5 --0.4 2.625 Units V V mA mA V V V Notes 1 1 0V VIN VCC Output(s) Disabled, 0V VIN VCC IOH = -1.0mA IOL = 1.0mA -5 -5 2.0 --2.375 1 1 1 DC CHARACTERISTICS Description Power Supply Current: Operating Power Supply Current: Standby Clock Running Standby Current NOTES: Symbol ICC ISB2 ISB4 Conditions Device Selected; All Inputs VIL or VIH; Cycle Time = TCYC MIN; VCC = MAX; Output Open Device Deselected; VCC = MAX; All Inputs VSS + 0.2 or VCC - 0.2; All Inputs Static; CK Frequency = 0 Device Deselected; VCC = MAX; All Inputs VSS + 0.2 or VCC - 0.2; Cycle Time = TCYC MIN Typ 166 MHZ 650 150 MHZ 600 60 120 133 MHZ 560 60 100 100 MHZ 500 60 80 Units mA mA mA Notes 1, 2 2 2 30 60 140 1. ICC is specified with no output current and increases with faster cycle times. ICC increases with faster cycle times and greater output loading. 2. Typical values are measured at 2.5V, 25C, and 10ns cycle time. BGA CAPACITANCE Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance NOTES: 1. This parameter is sampled. Symbol CL CO CA CCK Conditions TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz Typ 5 6 5 3 Max 7 8 7 5 Units pF pF pF pF Notes 1 1 1 1 White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC CHARACTERISTICS 166MHz 150MHz Parameter Clock Time Clock Access Time Output enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High Chip Select Setup to Clock High Address Hold to Clock high CKE Hold to Clock High Data Hold to Clock High Write Hold to Clock High Chip Select Hold to Clock High Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tCSS tAH tCEH tDH tWH tCSH Min 6.0 --1.5 1.5 0.0 --2.2 2.2 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 Max 3.5 3.5 ---3.0 3.0 -----------Min 6.7 --1.5 1.5 0.0 --2.5 2.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 Max 3.8 3.8 ---3.0 3.0 -----------133MHz Min 7.5 --1.5 1.5 0.0 --3.0 3.0 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 Max 4.2 4.2 ---3.5 3.5 ------------ WED2ZL64512S 100MHz Min 10.0 --1.5 1.5 0.0 --3.0 3.0 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 Max 5.0 5.0 ---3.5 3.5 -----------Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEX# is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE# low having been registered into the device. A Read cycle is defined by WE# High. Both cases must meet setup and hold times. (0C TA 70C, VCC = 2.5V 5%, Unless Otherwise Specified) Parameter Input Pulse Level Input Rise and Fall Time (Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load Value 0 to 2.5V 1.0V/ns 1.25V See Output Load (A) AC TEST CONDITIONS OUTPUT LOAD (A) DOUT Zo=50 RL=50 30pF* VL=1.25V (FOR tLZC, tLZOE, tHZOE, and tHZC) +2.5V DOUT 1538 1667 5pF* OUTPUT LOAD (B) *Including Scope and Jig Capacitance White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 3 TIMING WAVEFORM OF READ CYCLE tCH tCL WED2ZL64512S Clock tAS tAH A1 A2 Address tWS tWH WE0B WE1B tCSS tCSH CEx# OEB# tOE tLZOE tHZOE Q1-1 tCD tOH Q2-1 Data Out NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2, CE2#. Don't Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 4 TIMING WAVEFORM OF WRITE CYCLE tCH tCL WED2ZL64512S Clock Address A1 A2 WE0B# WE1B CEx# OEB# Data In tHZOE D1-1 D2-1 Data Out Q0-3 Q0-4 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE tCH WED2ZL64512S tCL Clock Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WE0B WE1B CEx# OEB# tOE tLZOE Data Out Q1 tDS tDH Q3 Q4 Q6 Q7 Data In D2 D5 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIG. 7 TIMING WAVEFORM OF CE# OPERATION tCH WED2ZL64512S tCL Clock tCYC Address A1 A2 A3 A4 A5 WE0B WE1B CEx# OEB# tOE tLZOE tHZC Q1 tCD tLZC Q4 Data Out Q2 tDS tDH Data In D3 D5 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PACKAGE DIMENSION: 119 BUMP PBGA 7.62 (0.300) TYP A B C D E F G H J K L M N P R T U WED2ZL64512S 1.90 (0.075) MAX 17.00 (0.669) TYP A1 CORNER 1.27 (0.050) TYP 23.00 (0.905) TYP 20.32 (0.800) TYP 1.27 (0.050) TYP 0.711 (0.028) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION COMMERCIAL TEMP RANGE (0C TA 70C) Part Number WED2ZL64512S35BC WED2ZL64512S38BC WED2ZL64512S42BC WED2ZL64512S50BC Configuration 512K x 64 512K x 64 512K x 64 512K x 64 tCD (ns) 3.5 3.8 4.2 5.0 Clock (MHz) 166 150 133 100 White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2001 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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